Samsung just revealed the blueprint for next-generation AI infrastructure. At the Future of Memory and Storage conference in Santa Clara, the chipmaker unveiled zHBM – a radical vertical memory architecture that stacks high-bandwidth memory directly above AI processors – alongside its 400-layer V10 BV-NAND and edge-optimized zNAND-O. The announcements position Samsung to directly address the memory bottleneck choking AI training and inference workloads as the industry races to build more powerful accelerators.

Samsung is betting that the future of AI memory doesn’t sit beside processors – it lives on top of them. The company’s zHBM concept model, unveiled at FMS 2026, vertically integrates high-bandwidth memory directly above AI accelerators, slashing the distance data travels between compute and storage. It’s a fundamental rethink of how AI systems are architected, and Samsung claims it’ll deliver roughly eight times the performance of HBM5 while cutting thermal resistance in half.

The physics are straightforward: shorter data paths mean faster transfers and lower power consumption. By stacking memory above the processor instead of mounting it alongside, zHBM minimizes interconnect latency – the milliseconds that add up when you’re training large language models or running inference at scale. Samsung says the architecture can pack more than 10 times the memory density of HBM5 while improving energy efficiency threefold, critical specs as AI workloads balloon and data centers grapple with power constraints.

What makes zHBM particularly interesting is its customization potential. Samsung designed the interlayer between memory and accelerator to accommodate customer-specific IP, letting hyperscalers and AI chip designers optimize performance for their exact use cases. That flexibility could prove decisive as companies like OpenAI, Google, and Meta build increasingly specialized AI infrastructure.

The company’s executives Jin-Yub Lee and Kyungryun Kim presented the vision during FMS 2026’s opening keynote, titled “Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture.” Their pitch centers on maximizing AI system performance while the industry confronts exponentially growing compute demands. Samsung plans to work closely with customers to optimize zHBM integration, though the company hasn’t announced timeline specifics for commercial availability.

Alongside zHBM, Samsung introduced zNAND-O, a next-gen NAND solution built on its V-NAND platform and developed in four-layer and eight-layer versions. The product targets edge AI environments where real-time processing matters – think autonomous vehicles, industrial robotics, and on-device inference. By combining high space efficiency with improved I/O performance and low latency, zNAND-O addresses a different bottleneck than zHBM: the storage demands of data-intensive applications running outside centralized data centers.

But the most immediate announcement is V10 BV-NAND, Samsung’s industry-first 400-plus-layer NAND architecture. Thirteen years after the company pioneered V-NAND at the 2013 Flash Memory Summit, it’s pushing vertical stacking to new extremes with wafer bonding technology that increases memory density 58% over the V9 generation. The jump isn’t just about cramming more layers – V10 BV-NAND also improves read, write, and I/O performance, supporting the high-capacity storage AI systems demand.

The bonding approach represents a manufacturing shift. Instead of etching ever-deeper vertical channels in a single wafer, Samsung bonds separately fabricated wafer layers together, sidestepping some of the physical limits that have constrained traditional V-NAND scaling. It’s a technique the industry has explored for years but Samsung is first to productize at this layer count.

Samsung also showcased its existing AI memory portfolio at FMS 2026, including HBM4E samples it began shipping to customers in May following February’s HBM4 mass production launch using 1c DRAM and 4-nanometer base die tech. The company displayed HBM5 models alongside LPDDR5X-PIM, its processing-in-memory solution that handles data processing within the memory itself to cut power consumption and data movement overhead.

The LPDDR5X-PIM tech is particularly relevant as AI inference moves to mobile and edge devices. By performing compute operations in-memory rather than shuttling data to a separate processor, the architecture reduces both latency and energy draw – crucial for battery-powered applications. Samsung claims it’s the industry’s first LPDDR memory with integrated processing capabilities.

On the enterprise storage front, Samsung featured its PM1763 and BM1773 solutions designed for AI data center workloads. These products complement the memory announcements by addressing the backend storage infrastructure that feeds training datasets and stores model checkpoints. As AI models scale into hundreds of billions of parameters, the storage layer becomes as critical as the memory hierarchy.

Samsung’s pitch extends beyond individual products. As the only integrated device manufacturer with in-house memory, foundry, and advanced packaging capabilities, the company positions itself as a one-stop shop for AI infrastructure. From initial design through mass production, Samsung argues it can deliver turnkey solutions that compress development cycles while optimizing performance and power efficiency – a compelling value proposition for customers trying to get AI chips to market quickly.

The company displayed roughly 30 memory and storage technologies in its AI cloud server-themed booth at FMS 2026, underscoring the breadth of its portfolio. It’s a direct challenge to competitors like Nvidia, which has been pushing its own memory and interconnect standards, and memory specialists like Micron and SK Hynix racing to ship next-gen HBM.

What Samsung didn’t announce: firm timelines for zHBM or zNAND-O commercialization, or pricing for any of the new technologies. The concept models signal intent and technical capability, but translating them into shipping products that AI system builders can actually deploy will determine whether Samsung maintains its memory leadership as the AI infrastructure buildout accelerates.

Samsung’s FMS 2026 announcements lay out a comprehensive vision for AI infrastructure that extends from vertical memory stacking to edge storage to enterprise solutions. The zHBM concept directly tackles the memory bandwidth crisis limiting AI accelerator performance, while V10 BV-NAND’s 400-layer milestone pushes storage density to new heights. But concepts need to become commercial products, and Samsung’s ability to manufacture these technologies at scale – and convince customers to adopt new architectures – will determine whether it maintains dominance in the AI memory race. With HBM4E already shipping and competitors pushing hard, the timeline from concept to production matters as much as the performance claims.